As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory device (DRAM) or static-random-access-memory device (SRAM), the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components.
One important technique for fabricating a device having a small surface area is to stack MOS transistors in a vertical arrangement. Typically, a first transistor is formed in the substrate having source, drain, and channel regions in the substrate and a gate electrode overlying the substrate surface. Then, a second transistor is formed in a thin-film layer overlying the first transistor. By adding an additional electrical component to the device, the thin-film transistor increases the functional capacity of a device while not consuming additional surface area.
Thin-thin transistors are especially useful in CMOS logic devices. For example, a CMOS inverter can be fabricated from an N-channel transistor in the substrate and P-channel, pull-up transistor in a thin-film layer overlying the N-channel transistor.
While thin-film transistors remain a useful design alternative for the formation of compact devices, they usually exhibit poor performance. Thin-film transistors are most often formed in an amorphous or polycrystalline material which does not conduct charge as well as a single crystal substrate. In addition, the fabrication process may result in contamination of the gate dielectric layer between the thin-film channel and the gate electrode. Contamination of the gate dielectric further impairs performance by causing flat-band voltage shifting.
Thin-film transistors also increase the topographic contrast of an integrated circuit device. Because thin-film transistors require an additional layer which must be formed over existing structures on the substrate surface, the total vertical height of the device above the substrate surface is increased. When metal leads are formed to interconnect the device with external portions of the integrated circuit, step coverage problems are encountered as the metal leads traverse the steep topography of the device. The severe topography can cause voids to develop in the leads resulting in loss of electrical conduction and device failure. Therefore, further development of thin-film transistors is necessary to meet the needs of high density semiconductor devices.